Verilog Interview Questions and Answers
Ques 6. Explain the 'case' statement in Verilog.
'case' statement is used for multi-way branching, similar to a switch statement in C/C++.
Example:
case(opcode) 4'b0000: result = A + B; 4'b0001: result = A - B; default: result = 8'b0; endcase
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Ques 7. What is the purpose of the 'parameter' keyword in Verilog?
'parameter' is used to declare constants that can be changed during elaboration and are visible throughout the module.
Example:
parameter WIDTH = 8;
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Ques 8. Explain the concept of 'blocking procedural assignments' in Verilog.
Blocking procedural assignments execute sequentially in the order they appear in the code.
Example:
a = b; c = a; // 'a' is assigned the value of 'b' before 'c' is assigned the value of 'a'
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Ques 9. What is the purpose of the 'fork-join' construct in Verilog?
'fork-join' is used for parallel execution of blocks within the same 'initial' or 'always' block.
Example:
initial begin fork begin // Block 1 $display("Block 1"); end join fork begin // Block 2 $display("Block 2"); end join end
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Ques 10. Explain the difference between '==', '===', and '==' in Verilog.
'==' and '===' are used for equality comparisons. '==' checks for bit-wise equality, while '===' checks for value equality, including unknown ('x') and high-impedance ('z').
Example:
if (a == b) // bit-wise equality if (a === b) // value equality
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