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Home / Interview Subjects / Verilog
WithoutBook LIVE Mock Interviews Verilog Related interview subjects: 12

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Know the top Verilog interview questions and answers for freshers and experienced candidates to prepare for job interviews.

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Freshers / Beginner level questions & answers

Ques 1

What is Verilog?

Verilog is a hardware description language (HDL) used to model electronic systems at various levels of abstraction.

Example:

module and_gate(output Y, input A, B); assign Y = A & B; endmodule
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Ques 2

What is the difference between 'reg' and 'wire' in Verilog?

'reg' is used for variables that can be assigned values inside an always block, while 'wire' is used for connecting different modules.

Example:

reg [7:0] data; wire [7:0] bus;
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Ques 4

What is the purpose of the 'parameter' keyword in Verilog?

'parameter' is used to declare constants that can be changed during elaboration and are visible throughout the module.

Example:

parameter WIDTH = 8;
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Ques 6

What is the purpose of the 'module' keyword in Verilog?

'module' is used to define the interface and behavior of a hardware module in Verilog.

Example:

module adder(input [3:0] A, B, output [4:0] Sum); // Module definition... endmodule
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Ques 10

Explain the purpose of the 'input' and 'output' keywords in Verilog module ports.

'input' is used to specify inputs to a module, and 'output' is used to specify outputs.

Example:

module myModule(input A, B, output Y); // Module definition... endmodule
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